1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and in particular, to an arrangement of power supply pads and data input/output pads in a semiconductor memory device. More particularly, the present invention relates to a layout of power supply pads, and data input/output buffers and peripheral circuits, and a multibit test circuit in a general-purpose DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
FIG. 33 schematically shows a chip layout of a conventional semiconductor memory device. In FIG. 33, the semiconductor memory device is formed on a semiconductor chip 1100, and includes four memory blocks MB1, MB2, MB3, and MB4. Each of memory blocks MB1-MB4 includes a plurality of memory cells. During the normal operation (during an external accessing), a one-bit memory cell is selected in each of memory blocks MB1-MB4, and data is written thereto or read therefrom (in the case of .times.4 bit configuration).
In the center region (a region between memory blocks MB1 and MB3 and memory blocks MB2 and MB4) of semiconductor chip 1100, arranged are pads for receiving external power supply voltage and ground voltage and for input/output of signals. Such a structure in which pads are arranged in the center region of a chip is known as a lead on chip (LOC) arrangement, in which the tips of lead frame are arranged on the chip, and the lead frame is connected at the respective tips to the pads arranged in the center region of the chip by wire bonding. Alignment of the pads in the chip center region allows an area occupied by the pads to be reduced as compared to a structure in which pads are arranged at a peripheral portion along both sides of semiconductor chip 1100, thereby improving the efficiency of use of the semiconductor chip.
In this pad arrangement, power supply pads VC1 and VC2 are usually arranged at opposite ends in the center region of semiconductor chip 1100 in order to maintain compatibility of pins with a semiconductor memory device of the previous generation for example. Data input/output pads DQ1-DQ4 are collectively arranged adjacent to one power supply pad VC1. The other power supply pad VC2 supplies power supply voltage to circuits other than the data input/output circuits. In the figure, power supply pads VC1 and VC2 are shown supplying power supply voltage Vcc. Similarly, ground pads for supplying ground voltage Vss are arranged adjacent to power supply pads VC1 and VC2, respectively. However, for simplicity of illustration, the ground pads are not shown.
Data input/output pads DQ1-DQ4 carry out transmission and reception of data to and from memory blocks MB1-MB4 through internal data buses 1102a-l102d, respectively. Although not clearly shown in FIG. 33, data input/output buffers are provided adjacent to respective data input/output pads DQ1-DQ4. These data input/output buffers are made operative in response to supply of operation power supply voltage from power supply pad VC1 and ground voltage. By providing an operation power source for the data input/output buffers separately from that for the other circuits, power supply voltage and ground voltage used upon input/output of data are stabilized, and data input/output operation (data output operation in particular) is stabilized (data is input/output stably without the influence of power supply noise), and is increased in speed (charge/discharge operation is carried out at a high speed due to alleviation of the load of a power supply circuit).
The data input/output buffers are arranged adjacent to data input/output pads DQ1-DQ4. These data input/output buffers operate with power supply voltage Vcc supplied from the power supply pad VCI in common. Since a plurality of (four in FIG. 33) data input/output buffers are coupled to one power supply pad, the load of the power supply pad (power supply line) increases. The current supplying capability of power supply pad VC1 is determined according to the external specification. Therefore, when the number of data input/output buffers (data output buffers in particular) connected to the power supply pad VC1 increases, each data input/output buffer cannot be supplied with current of a sufficient magnitude from power supply pad VC1 stably. As a result, power supply voltage and ground voltage vary, the data input/output buffers cannot charge/discharge respective output nodes at a high speed, and these buffers cannot operate at a high speed. During the data output operation in particular, when variation of power supply voltage causes the operation speed of the output buffers to decrease, a timing at which valid output data appear at external pin terminals through the pads is delayed, and data cannot be read out at a high speed.
Power supply pad VC2 provided at a periphery of the center region of semiconductor chip 1100 is used for supplying power supply voltage to peripheral circuits. Although not clearly shown in FIG. 33, the peripheral circuits are distributedly arranged on semiconductor chip 1100. Therefore, the length of a power supply line from power supply pad VC2 to each peripheral circuit becomes longer, causing reduction of power supply voltage by interconnection line resistance, instability of power supply voltage or the like. As a result, the peripheral circuits cannot operate stably.
In order to shorten the power supply lines from power supply pad VC1 to the data input/output buffers, and to decrease the load of the power supply lines as much as possible, the data input/output buffers and data input/output pads DQ1-DQ4 are collectively arranged in the vicinity of power supply pad VC1. Therefore, internal data line 1102a between memory block MB1 and data input/output pad DQ1 and internal data line 1102b between memory block MB2 and data input/output pad DQ2 are larger in length than internal data line 1102c between memory block MB3 and data input/output pad DQ3 and internal data line 1102d between memory block MB4 and data input/output pad DQ4. In this case, the interconnection line resistances and the parasitic capacitances of internal data lines 1102a and 1102b become larger than those of internal data lines 1102c and 1102d, and the signal propagation delay in internal data lines 1102a and 1102b becomes larger than that in internal data lines 1102c and 1102d, hampering high speed accessing. In particular, at the time of data reading, a timing at which data read out from memory blocks MB1 and MB2 appear and are determined at pads DQ1 and DQ2 is delayed from a timing at which memory cell data read out from memory blocks MB3 and MB4 appear and are determined at pads DQ3 and DQ4. It is necessary to decide an output data determination timing by the delayed timing, resulting in longer access time at the time of data reading.
Similarly, at the time of data writing, internal write data is generated from write data which appear on pads DQ1-DQ4 in response to a write pulse (generated in response to a write enable signal), and transmitted to respective memory blocks MB1-MB4 through internal data lines 1102a-l102d. In this case, a timing at which write data is written in memory blocks MB1 and MB2 is delayed from a timing at which write data is written in memory blocks MB3 and MB4, resulting in a longer data writing time.
As shown in FIG. 34, in the case of a conventional arrangement of data input/output pads, peripheral pads PD1-PDn receiving address signals and clock signals (external control signals such as a row address strobe signal RAS and a write enable signal WE), and a master control circuit 1110 receiving internal signals from peripheral pads PD1-PDn and generating signals controlling accessing operations to memory blocks MB1-MB4 are provided in a region other than a region for forming data input/output pads DQ1-DQ4 in the center region of semiconductor chip 1100. Buffers provided corresponding to pads PD1-PDn operate in reception of power supply voltage from power supply pad VC2. Usually, peripheral pads PD1-PDn are arranged alignedly. An internal signal from peripheral pad PD1 is applied to master control circuit 1110 through a signal line 1112, and an internal signal from peripheral pad PDn is applied to master control circuit 1110 through a signal line 1113.
Master control circuit 1110 provides necessary control signals for memory blocks MB1-MB4, respectively, and generates signals defining data input/output timings of the data input/output buffers provided corresponding to data input/output pads DQ1-DQ4. Generally, the DRAM strobes an address signal applied to an address input pad in response to the falling of row address strobe signal RAS, and generates an internal row address signal. Usually, for the address signal, a set-up time and a hold time are determined with respect to the falling edge of the signal RAS. When signal lines 1112 and 1113 are different in length from each other as shown in FIG. 34, these signal lines 1112 and 1113 have different signal propagation delays from each other, and therefore, it is necessary to set the set-up time and the hold time for the worst case. This prevents an implementation of earlier internal operation start timing and high speed operation. Further, the difference in distances from master control circuit 1110 to memory blocks MB1-MB4 prevents operation timings of memory blocks MB1-MB4 from being common, and accessing time becomes longer for the worst case.